`timescale 1ns / 1ps

module test_replication(
    input clk,
    input rst,
    input [3:0] bus_a,
    input [3:0] bus_b,
    output [7:0] data_out,
    output [3:0] ctrl_out
);

// Test module with various replication syntax examples
sub_module_1 u_sub1 (
    // Simple replication: 4 times clk signal
    .clk_bus    ({4{clk}}),
    
    // Replication with bit select
    .data_in    ({2{bus_a[3:0]}}),
    
    // Mixed: concatenation with replication
    .mixed      ({rst, {3{clk}}, bus_a}),
    
    // Nested: replication inside concatenation
    .complex    ({bus_a, {2{bus_b}}, rst})
);

// Test module with single replication
sub_module_2 u_sub2 (
    .enable_bus ({8{rst}}),
    .data_out   (data_out)
);

// Test module with bit replication
sub_module_3 u_sub3 (
    .ctrl       ({2{bus_a[1:0]}}),
    .status     (ctrl_out)
);

endmodule

// Dummy sub-modules for testing
module sub_module_1(
    input [3:0] clk_bus,
    input [7:0] data_in,
    input [7:0] mixed,
    input [11:0] complex
);
endmodule

module sub_module_2(
    input [7:0] enable_bus,
    output [7:0] data_out
);
endmodule

module sub_module_3(
    input [3:0] ctrl,
    output [3:0] status
);
endmodule
